1. Field of the Invention
This invention relates to a semiconductor integrated circuit capable of reducing a power consumption by controlling supply of power for an internal circuit in accordance with an active state and a sleep state of the internal circuit.
2. Description of the Prior Art
FIG. 4 is a semiconductor integrated circuit which is disclosed in JP-A 11-214962(1999). The semiconductor integrated circuit comprises: p-channel field effect transistors (hereinafter, referred to as pMOS transistors) QA1 to QA3, an n-channel field effect transistor (referred to as an nMOS transistor) QB1, and diodes D1 and D2. The pMOS transistor QA1 is connected between a power supply line VDD1 and a virtual or pseudo power supply line VA1 to be used as a switch for a power supply. The pMOS transistor QA2 is connected between the power supply line VDD1 and a substrate power supply line VA2. The pMOS transistor QA3 is connected between the substrate power supply line VA2 and a power supply line VDD2. The nMOS transistor QB1 is connected between a power supply line GND and a virtual power supply line VB1 to be used as a switch for a power supply. The diode D1 is connected between the virtual power supply line VA1 and the substrate power supply line VA2. The diode D2 is connected between the power supply line GND and the virtual power supply line VB1. An internal circuit is connected between the virtual power supply lines VA1 and VB1 which feed operation power supplies to the internal circuit. The internal circuit includes a latch circuit having pMOS transistors Q3 and Q4 and nMOS transistors Q5 and Q6 each having a threshold voltage lower in absolute value than each of the transistors QA1 to QA3 and QB1.
The power supply line VDD1 is supplied with a voltage having a voltage value LVDD. The power supply line VDD2 is supplied with a voltage having a voltage value HVDD which is higher than the voltage value LVDD. The transistors QA1, QA2, and QB1 are controlled in response to control signals CS1 and CSB1, and are simultaneously put into ON state when the internal circuit is at an active state, while the transistors QA1, QA2, and QB1 are put into OFF state when the internal circuit is at a sleep state. The transistor QA3 is controlled by the control signal CS1, and is put into OFF state when the internal circuit at the active state, while the transistor QA3 is put into ON state when the internal circuit is at the sleep state.
A substrate potential is applied by a reverse bias to a source of each of the transistors Q3 to Q6 by the diodes D1 and D2 so that the absolute value of the threshold voltage may increase in each of the transistors Q3 to Q6 when the internal circuit is especially at the sleep state. In a case where the internal circuit has a sequence circuit such as latch circuits, it is possible to reduce a leakage current when the internal circuit is at the sleep state, without losing data which is held in the sequence circuit on the active state.
It will be assumed that potential differences V1 and V2 occur on the basis of the diodes D1 and D2, respectively, in the semiconductor integrated circuit illustrated in FIG. 4. The reduction ratio varies in concern to the leakage current on the sleep state on the basis of the potential differences V1 and V2. As the potential differences V1 and V2 become greater and greater, a body effect becomes greater, which enhances the reduction ratio of the leakage current. On the other hand, it is necessary to supply the internal circuit with a supply voltage in which the internal circuit can hold the data therein on the sleep state. Therefore, it is necessary to determine the potential differences V1 and V2 so that the voltage (HVDDxe2x88x92V1xe2x88x92V2) becomes greater than the supply voltage which is supplied to the internal circuit on the sleep state. It will be assumed that the voltage value HVDD is equal to 3.3 V which is usually used as an I/O supply voltage which is an input-output buffer connected between the internal circuit and external signal pins.
Furthermore, it will be assumed that the supply voltage is equal to 0.9 V which is supplied to the internal circuit on the sleep state. When the potential difference V1 is equal to the potential difference V2, each of the potential differences V1 and V2 becomes 1.2 V in maximum. As a result, it is possible to reduce the leakage current in 1.5 to 2 orders of magnitude. However, it is also necessary to lower the I/O supply voltage for reduction of the power consumption. For example, the I/O supply voltage of 2.5 V is used in a specific one of the semiconductor integrated circuits. In a case where the voltage value HVDD is equal to 2.5 V when the supply voltage of 0.9 V is supplied to the internal circuit on the sleep state, each of the potential differences V1 and V2 becomes 0.8 V in maximum. The leakage current merely reduces in an order of magnitude. In other words, there is a drawback in which the reduction ratio of the leakage current decreases inasmuch as the reverse bias is shallow low when the voltage value HVDD is brought to a low voltage.
It is an object of this invention to provide a semiconductor integrated circuit capable of reducing a leakage current with holding data in an internal circuit on a sleep state, even if a supply voltage to be used on the sleep state is lowered.
A semiconductor integrated circuit according to this invention comprises a first switch for supplying a first voltage to a first power supply line when the first switch is put into ON state and a voltage dropping circuit, arranged between the first power supply line and a second power supply line, for supplying the first power supply line with a voltage which is obtained by dropping the voltage of the second power supply line, when the first switch is put into OFF state. The semiconductor integrated circuit further comprises a third power supply line having a second voltage which is lower than the first voltage, a fourth power supply line, and a voltage generating circuit for generating a third voltage lower than the second voltage, to supply the third voltage to the fourth power supply line when the first switch is put into OFF state. The voltage generating circuit generates a high voltage higher than the third voltage, to supply the high voltage to the fourth power supply line when the first switch is put into ON state.
In an internal circuit, a p-channel field effect transistor has a source terminal and a substrate terminal which are connected to the first power supply line and the second power supply line, respectively. On the other hand, an n-channel field effect transistor has a source terminal and a substrate terminal which are connected to the third power supply line and the fourth power supply line, respectively.
Inasmuch as the third power supply line has the second voltage, the voltage of the third power supply line does not rise on the sleep state in comparison with the active state. Accordingly, it is possible for the internal circuit to maintain the voltage between the first and the third power supply lines, at a voltage in which the internal circuit can keep the data held on the active state, when the internal circuit is at the sleep state. Furthermore, it is possible to reduce the leakage current on the sleep state in the n-channel field effect transistor inasmuch as the substrate potential is applied as the reverse bias to the n-channel field effect transistor of the internal circuit so that the absolute value of the threshold voltage increases in the n-channel field effect transistor, when the internal circuit is at the sleep state. On the other hand, the leakage current decreases in the p-channel field effect transistor by operation of the voltage dropping circuit, when the internal circuit is at the sleep state.
The voltage generating circuit comprises an oscillator for generating an oscillation signal having a predetermined amplitude when the first switch is put into OFF state. The oscillator stops generation of the oscillation signal when the first switch is put into ON state. The voltage generating circuit further comprises a charge pump for generating the third voltage in accordance with the oscillation signal. Therefore, the oscillator stops the oscillation when the internal circuit is at the active state. It is possible to save the power consumption based on the oscillation.
The voltage generating circuit further comprises a level detector for comparing a predetermined voltage with the voltage of the fourth power supply line, to produce a comparison result between the predetermined voltage and the voltage of the fourth power supply line. When the oscillator generates the oscillation signal in accordance with the comparison result produced by the level detector, it is possible to generate the third voltage with stopping the oscillation of the oscillator, even though the internal circuit is at the sleep state. As a result, it is possible to save the power consumption caused by the oscillation.
The voltage generating circuit further comprises a switch circuit connected to the third and the fourth power supply lines. The switch circuit is put into ON state when the first switch is put into ON state. The voltage of the fourth power supply line quickly varies to the second voltage when the internal circuit is at the active state.
The semiconductor integrated circuit further comprises a voltage control circuit for supplying the second power supply line with a fourth voltage higher than the first voltage which is supplied to the first power supply line on putting the first switch into ON state, when the first switch is put into OFF state.
More specifically, the voltage control circuit comprises a second switch, connected to the second power supply line, for being put into ON state when the first switch is put into ON state. The voltage control circuit further comprises a third switch, connected to the second power supply line, for being put into ON state to supply the fourth voltage to the second power supply line. The first switch may have first and second terminals which are connected to the second switch and the first power supply line, respectively. The first terminal is supplied with a supply voltage. Alternatively, the voltage control circuit comprises a second switch, connected to the first and second power supply lines, for being put into ON state when the first switch is put into ON state. The voltage control circuit further comprises a third switch, connected to the second power supply line, for being put into ON state to supply the fourth voltage to the second power supply line. In this case, the first switch may have a first terminal which is supplied with a supply voltage. The first switch may have a second terminal which is connected to the second switch and the first power supply line.
The voltage dropping circuit includes a diode or a plurality of diodes connected to one another in series. The diode or the diodes are connected between the first and the second power supply lines. Alternatively, the voltage dropping circuit may include a field effect transistor or a plurality of field effect transistors connected to one another in series, instead of the diode or the diodes. When the voltage dropping circuit includes the field effect transistor or the field effect transistors, it is possible to adjust the potential difference between the first and the second power supply lines on varying the voltage supplied to each substrate electrode of the field effect transistor or the field effect transistors.